Leadless plastic chip carrier with etch back pad singulation

ABSTRACT

A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This is a continuation-in-part of U.S. patent application Ser.No. 09/288,352, filed Apr. 8, 1999, which is a continuation-in-part ofU.S. patent application Ser. No. 09/095,803, filed Jun. 10, 1998.

FIELD OF THE INVENTION

[0002] The present invention relates in general to integrated circuitpackaging, and more particularly to an improved process for fabricatinga leadless plastic chip carrier which includes a post mold etch backstep and unique contact pad and die attach pad design features.

BACKGROUND OF THE INVENTION

[0003] According to well known prior art IC (integrated circuit)packaging methodologies, semiconductor dice are singulated and mountedusing epoxy or other conventional means onto respective die pads (attachpaddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packagesincorporate inner leads which function as lands for wire bonding thesemiconductor die bond pads. These inner leads typically require moldlocking features to ensure proper positioning of the leadframe stripduring subsequent molding to encapsulate the package. The inner leadsterminate in outer leads that are bent down to contact a mother board,thereby limiting the packaging density of such prior art devices.

[0004] In order to overcome these and other disadvantages of the priorart, the Applicants previously developed a Leadless Plastic Chip Carrier(LPCC). According to Applicants' LPCC methodology, a leadframe strip isprovided for supporting up to several hundred devices. Singulated ICdice are placed on the strip die attach pads using conventional diemount and epoxy techniques. After curing of the epoxy, the dice are goldwire bonded to peripheral internal leads. The leadframe strip is thenmolded in plastic or resin using a modified mold wherein the bottomcavity is a flat plate. In the resulting molded package, the die pad andleadframe inner leads are exposed. By exposing the bottom of the dieattach pad, mold delamination at the bottom of the die paddle iseliminated, thereby increasing the moisture sensitivity performance.Also, thermal performance of the IC package is improved by providing adirect thermal path from the exposed die attach pad to the motherboard.By exposing the leadframe inner leads, the requirement for mold lockingfeatures is eliminated and no external lead standoff is necessary,thereby increasing device density and reducing package thickness overprior art methodologies. The exposed inner leadframe leads function assolder pads for motherboard assembly such that less gold wire bonding isrequired as compared to prior art methodologies, thereby improvingelectrical performance in terms of board level parasitics and enhancingpackage design flexibility over prior art packages (i.e. custom trimtools and form tools are not required). These and several otheradvantages of Applicants' own prior art LPCC process are discussed inApplicants' co-pending patent application Ser. No. 09/095,803, thecontents of which are incorporated herein by reference.

[0005] Applicants' LPCC production methodology utilizes saw singulationto isolate the perimeter I/O row as well as multi-row partial leadisolation. Specifically, the leadframe strip is mounted to a wafer sawring using adhesive tape and saw-singulated using a conventional wafersaw. The singulation is guided by a pattern of fiducial marks on thebottom side of the leadframe strip. Also, special mold processingtechniques are used to prevent the mold flow from bleeding onto thefunctional pad area and inhibiting electrical contact. Specifically, theexposed die pad surface is required to be deflashed after molding toremove any molding compound residue and thereby allow the exposed leadsand die attach pad to serve as solder pads for attachment to themotherboard.

[0006] According to Applicant's co-pending U.S. patent application Ser.No. 09/288,352, the contents of which are incorporated herein byreference, an etch back process is provided for the improved manufactureof the LPCC IC package. The leadframe strip is first subjected to apartial etch on one or both of the top and bottom surfaces in order tocreate a pattern of contact leads (pads) and a die attach pad (paddle).After wire bonding the contacts to a singulated semiconductor die,followed by overmolding and curing of the mold, the leadframe strip isexposed to a second full etch immersion for exposing the contact pads inan array pattern (i.e. multi-row) or perimeter pattern (i.e. singlerow), as well as the die attach pad. In the case of a package withmulti-row I/O leads, this etch back step eliminates the requirement fortwo additional saw singulation operations (i.e. to sever the inner leadsfrom the outer leads), and in both the single-row and multi-rowconfigurations, the etch back step eliminates post mold processing steps(e.g. mold deflashing) and ensures superior device yield over theprocessing technique set forth in Applicants' prior application Ser. No.09/095,803. Additionally, using this technique allows for higher I/O paddensity and also allows for pad standoff from the package bottom whichreduces stress in the solder joint during PCB temp cycling. Further, thetechnique allows for the use of a pre-singulation strip testingtechnique given that the electrical I/O pads are now isolated from eachother and testing in strip can take place. This feature greatlyincreased the handling and throughput of the test operation.

[0007] Other prior art references teach the concepts of etching back asacrificial substrate layer to expose contact pads and die attachpaddle, such as U.S. Pat. Nos. 4,530,152 (Roche et al); 5,976,912(Fukutomi, et al); 6,001,671 (Fjelstad) and Japanese patent applicationno. 59-208756 (Akiyama).

SUMMARY OF THE INVENTION

[0008] According to the present invention, Applicant's etch-back LPCCprocess has been modified to provide additional design features.Firstly, an etch barrier is provided as the first layer of the contactpads and die attach pad, and the contact pads are formed to a “rivet”head shape for improved interlocking and the die attach pad is formedwith an interlock pattern for improved alignment with the semiconductordie. Improved electrical performance is enjoyed over the above discussedprior art designs by incorporation of a ground ring on the die attachpad to which multiple ground pads on the die are parallel bonded. Theincorporation of a ground ring on the die attach pad provides a constantdistance between the ground ring and the ground pads to which the groundring is wire bonded. The ground ring is then bonded out to only one ofthe external I/O pads.

[0009] According to a further embodiment of the invention, twoconcentric rings are provided to allow for both power and ground usingonly a single I/O pad for each.

[0010] According to an additional embodiment, an etch down cavity isprovided for solder ball attachment.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A detailed description of the invention is provided herein belowwith reference to the following drawings, in which:

[0012]FIGS. 1A - 1I show processing steps for manufacturing a LeadlessPlastic Chip Carrier (LPCC) with top and bottom partial etch resultingin a bottom etch cavity, according to a first embodiment of Applicants'prior art process;

[0013]FIGS. 2A - 2G show processing steps for manufacturing a LeadlessPlastic Chip Carrier (LPCC) with top and bottom partial etchincorporating standoff, according to a second embodiment of Applicants'prior art process;

[0014]FIGS. 3A - 3H show processing steps for manufacturing a LeadlessPlastic Chip Carrier (LPCC) with top side partial etch and solder ballattachment, according to a third embodiment of Applicants' prior artprocess;

[0015]FIGS. 4A - 4I show processing steps for manufacturing a LeadlessPlastic Chip Carrier (LPCC) with top side partial etch incorporatingstandoff, according to a fourth embodiment of Applicants' prior artprocess;

[0016]FIGS. 5A - 5J show processing steps for manufacturing a LeadlessPlastic Chip Carrier (LPCC) with bottom side partial etch, according toa fifth embodiment of Applicants' prior art process;

[0017]FIGS. 6A - 6H show processing steps for manufacturing a LeadlessPlastic Chip Carrier (LPCC) with etch back and special attachmentfeatures, according to the present invention;

[0018]FIG. 7 is a bottom plan view of a single row IC packagemanufactured in accordance with the process of FIGS. 6A - 6H; and

[0019]FIGS. 8A and 8B are bottom plan views of array type IC packagesmanufactured in accordance with the process of FIGS. 6A - 6H.

[0020]FIG. 9 is a bottom plan view of an array type IC package accordingto the present invention, showing a pair of concentric rings.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

[0021] Applicants' prior Leadless Plastic Chip Carrier with Etch BackSingulation (LPCCEBS) process as described in copending application Ser.No. 09/288,352 is an improvement over Applicants' LPCC process as setforth in co-pending application Ser. No. 09/095,803. The presentinvention relates to an improvement in Applicants' prior LPCCmethodology. Before describing details of the improvement according tothe present invention, reference will be made to FIGS. 1 to 5 which setforth Applicants' LPCCEBS process. Where possible, the same referencenumerals have been used in this application to denote identical featuresdescribed in Applicants' earlier applications. Reference may be had toApplicants' co-pending applications for additional details concerningprocessing steps which are common to Applicants' processes.

[0022]FIGS. 1A - 1I show steps in the manufacture of an LPCCEBSaccording to a first embodiment of the invention disclosed in copendingapplication Ser. No. 09/288,352—namely, with top and bottom side partialetch and bottom etch cavity.

[0023] With reference to FIG. 1A, an elevation view is provided of acopper panel substrate which forms the raw material of the leadframestrip 100. As discussed in greater detail in Applicants' co-pendingapplication Ser. No. 09/095,803, the leadframe strip 100 is divided intoa plurality of sections, each of which incorporates a plurality ofleadframe units in an array (e.g. 3×3 array, 5×5 array, etc.). Only onesuch unit is depicted in the elevation view of FIG. 1A, portions ofadjacent units being shown by stippled lines.

[0024] The leadframe strip 1100 is subjected to a partial etch on bothtop and bottom sides (FIG. 1B) to pattern the contact pads 203 and dieattach pad 202. Next, the strip 1100 is plated with silver (Ag) ornickel/palladium (Ni/Pd) to facilitate wire bonding (FIG. 1C).

[0025] A singulated semiconductor die 206 is conventionally mounted viaepoxy (or other means) to the die attach pad 202, and the epoxy iscured. Gold wires 205 are then bonded between the semiconductor die 206and peripheral leads or contacts 203. The leadframe 100 is then moldedusing a modified mold with the bottom cavity being a flat plate, andsubsequently cured, as discussed in Applicants' application Ser. No.09/095,803. The leadframe 1100 after the foregoing steps is as shown inFIG. 1D, which includes overmold 401 of cured plastic or epoxy.

[0026] Next, rather than post-mold deflashing, as performed according toApplicants' prior methodology, a wet film layer of photoresist 402 isprinted onto the bottom of leadframe 100 so as to cover portions of thebottom surface which are to be protected from etchant (i.e. positivephotoresist). The photoresist is then developed (cured) usingconventional means (FIG. 1E).

[0027] The leadframe 100 is then subjected to a final etching via fullimmersion (FIG. 1F) which exposes an array or perimeter pattern ofexposed contact pads 203 and the die attach pad 206.

[0028] The photoresist layer 402 is then stripped using conventionalmeans (FIG. 1G), resulting in small protrusions below the molded bodyfor contact pads 203. After this etch back step, the leadframe strip 100is coated with either electroless gold or solder dip to facilitate padsoldering (FIG. 1H). Alternatively, barrel plated solder or chemicallypassivated bare copper may be used for terminal finishing.

[0029] At this stage of manufacture, the pads 203 and 202 are fullyisolated and exposed. Singulation of the individual units from the fullleadframe array strip 100 may then be performed either by sawsingulation or die punching (FIG. 1I).

[0030] The embodiment of FIGS. 2A - 2G is similar to that of FIGS. 1A -1I, except that the partial etch (FIG. 2B) is a “mirror image” partialetch which results in a “standoff” structure, rather than being anoffset pattern as shown in FIG. 1B. Consequently, no photoresistapplication is required following the mold step (FIG. 2D) and prior tothe final etch back step (FIG. 2E).

[0031] Applicants' LPCC fabrication process may alternatively utilize asingle side first partial etch, as shown in FIGS. 3 and 4. FIGS. 3A - 3Hshow a single side partial etch process wherein, after the final fullimmersion etch and electroless gold plating (FIGS. 3E and 3F), the pads203 are above the mold line so that solder balls 203A are required to beattached in order to allow board mounting. FIGS. 4A - 4I show a singleside first partial etch with standoff (similar in this respect to theprocess of FIG. 2). A layer of photoresist 402 is applied (FIG. 4E) andpatterned, prior to the final etch back step (FIG. 4F). In otherrespects, the steps depicted in FIGS. 3 and 4 are similar to the stepsdiscussed above and illustrated in FIGS. 1 and 2, respectively.

[0032]FIGS. 5A - 5J show steps according to the etch back process ofApplicants' prior invention, for fabricating an LPCC with multi-rowpartial lead isolation. In FIG. 5A, a copper panel is provided, to whichphotoresist 502 is applied and patterned for a “first level” connect(FIG. 5B). An electrolytic plat of Cu/Ni/Au is applied to portions ofthe leadframe strip not covered by photoresist (FIG. 5C). Thephotoresist is then stripped (FIG. 5D), resulting in the structure ofFIG. 5D with contact pads 203 and attach pad 202.

[0033] A layer of negative photoresist 504 is applied and patterned fora “second level” connect (FIG. 5E). A pre-etch step is then performed(FIG. 5F) to create contact and attach pad protrusions on the bottom ofthe structure. The photoresist 504 is then stripped and the structure iscleaned (FIG. 5G).

[0034] Next, the semiconductor 206 is attached to the pad 202, gold wirebonds 203 are attached to the multi-row leads 203 and the structure isencapsulated as discussed above in mold 401, such that the contact padand attach pad protrusions remain exposed (FIG. 5H). A final etch backis performed (FIG. 5J) and the individual units are singulated. It willbe noted that the steps in Applicants' prior LPCC process of sawsingulating between the inner and outer rows of leads, is eliminated.Also, as with the embodiments of FIGS. 1 to 4, post mold deflashing andcleaning has been eliminated.

[0035] Having thus described Applicants' prior LPCC and LPCCEBSmethodologies, reference will now be made to FIGS. 6, 7 and 8 showingthe improvements which constitute the present invention.

[0036] With reference to FIG. 6A, an elevation view is provided of acopper panel substrate which forms the raw material of leadframe strip100 having thickness of approximately 5 mils. As discussed in greaterdetail in Applicants' co-pending application Ser. No. 09/095,803, theleadframe strip is divided into a plurality of sections, each of whichincorporates a plurality of leadframe units in an array (e.g. 3×3 array,5×5 array, etc.). Only one such unit is depicted in the elevation viewof FIG. 6A, portions of adjacent units being shown by stippled lines.

[0037] The leadframe strip 100 is covered with a photoresist mask 102(FIG. 6B) in order to mask predetermined areas from subsequent multipledeposition steps (FIG. 6C). The leadframe strip 100 is then subjected toan etching process to create the contact pads 203, power or ground ringattachment 204 and die attach pad 202 (FIG. 6D). The ring 204 can beeither a power or a ground ring 204.

[0038] One feature of the present invention is the deliberate depositionof the photoresist mask 102 in only a very thin layer (e.g. 2 mils) suchthat each contact pad 203 is plated up into a columnar shape as it flowsover the photoresist mask, resulting in a “mushroom cap” or rivet shape(FIGS. 6D and 6F). The shape of the contact pads 203 is such that theyare capable of being locked into the mold body thereby providingsuperior board mount reliability. It is also contemplated that a“funnel” shape may be provided for the contact pads 203 by incorporatingan angle on the photoresist mask.

[0039] As shown in FIG. 6D, several deposition and etching options areavailable. According to options A-1 and A-2, a layer of flash Cu (50microinches) is provided over the Cu substrate for creating an etch downcavity following post etching (discussed in greater detail below withreference to FIG. 6F) for attaching solder balls (also discussed belowwith reference to FIG. 6G). An etch barrier layer of Au (20 microinches)is then deposited, followed by layers of Ni (40 microinches), and Cu(3-4 mils). According to option A-1, final layers of Ni (40 microinches)and Au (20 microinches) are deposited whereas in Option A-2 a finallayer of Ag is deposited (100-300 microinches).

[0040] In plating Options B-1 and B-2, the initial flash Cu depositionis omitted, and in Options C-1 and C-2 the etch barrier of Au andsubsequent Ni deposition are replaced by an etch barrier of tin (100-300microinches).

[0041] A singulated semiconductor die 206 is conventionally mounted viaepoxy (or other means) to the die attach pad 202, and the epoxy iscured. Gold wires 205 are then bonded between the semiconductor die 206and peripheral leads or contacts 203. The leadframe 100 is then moldedusing a modified mold with the bottom cavity being a flat plate, andsubsequently cured, as discussed in Applicants' application Ser. No.09/095,803. The leadframe 100 after the foregoing steps is as shown inFIG. 6E, which includes overmold 401 of cured plastic or epoxy (0.8 mm).

[0042] The leadframe 100 is then subjected to a final alkaline etchingvia full immersion (FIG. 6F) which exposes an array or perimeter patternof exposed contact pads 203, power/ground ring 204 and the die attachpad 206. According to Option A, an etch down cavity 203B is left afteretching away the flash Cu, for attachment of solder balls 203A tocontact pads 203, as shown in FIG. 6G. At this stage of manufacture, thepower/ground ring 204 and die attach pad 202 (which also functions as aground plane) are fully isolated and exposed. Singulation of theindividual units from the full leadframe array strip 100 may then beperformed either by saw singulation or die punching resulting in thefinal configuration of FIG. 6H. Since the entire LPCC contains shortcircuit connections prior to singulation, it is contemplated that themultiple circuits may be gang tested before singulation.

[0043] The fabrication process of the present invention mayalternatively omit the solder ball attachment step, as shown in OptionsB and C.

[0044]FIG. 7 is a bottom plan view of the assembled IC package accordingto the present invention, with a single row of I/O contacts, while FIGS.8A and 8B show array type packages manufactured in accordance with theprocess of FIGS. 6A - 6H. In FIG. 8A, the contact pads 203 are round,whereas in FIG. 8B the contact pads are rectangular. The power/groundring 204 and the interlocking pattern of the die attach pad/ground plane202, are clearly shown.

[0045]FIG. 9 is a bottom plan view according to yet another embodimentof the present invention, with three rows of contact pads 203, and apair of concentric rings 204. In the present embodiment, one of therings 204 is a power ring and the other is a ground ring.

[0046] Other embodiments of the invention are possible. For example, thetwo rings may be present, one being a power ring and the other being aground ring. All such embodiments are believed to be within the sphereand scope of the invention as set forth in the claims appended hereto.

We claim:
 1. A process for fabricating a leadless plastic chip carrier,comprising the steps of: depositing a mask on a first surface of aleadframe strip to define at least one row of contact pads and apower/ground ring adjacent a die attach pad of said leadless plasticchip carrier; depositing a plurality of layers on portions of saidsurface exposed by said mask for creating said at least one row ofcontact pads, said power/ground ring and said die attach pad; dissolvingaway said mask; mounting a semiconductor die to said die attach pad onsaid top surface and wire bonding said semiconductor die to said contactpads; encapsulating said top surface of said leadframe strip in amolding material; etching back a bottom surface of said leadframe stripfor exposing said contact pads and said die attach pad; and singulatingsaid leadless plastic chip carrier from said leadframe strip.
 2. Theprocess of claim 1 , wherein said step of depositing said plurality oflayers includes an initial deposition of flash Cu which is etched awayduring step of etching back said bottom surface to create a cavity, andfurther including a step of attaching solder balls to said contact padsexposed as a result of said step of etching back said bottom surface ofsaid leadframe strip.
 3. The process of claim 2 , wherein said initialdeposition of flash Cu is followed by depositing layers of Au, Ni, Cu,Ni and Au.
 4. The process of claim 2 , wherein said initial depositionof flash Cu is followed by depositing layers of Au, Ni, Cu and Ag. 5.The process of claim 1 , wherein said step of depositing said pluralityof layers includes depositing successive layers of Au, Ni, Cu, Ni andAu.
 6. The process of claim 1 , wherein said step of depositing saidplurality of layers includes depositing successive layers of Au, Ni, Cu,and Ag.
 7. The process of claim 1 , wherein said step of depositing saidplurality of layers includes depositing successive layers of Tin, Cu, Niand Au.
 8. The process of claim 1 , wherein said step of depositing saidplurality of layers includes depositing successive layers of Tin, Cu,and Ag.
 9. A leadless plastic chip carrier, comprising: a semiconductordie mounted to a ground plane; at least one row of contact padscircumscribing said ground plane; a power/ground ring intermediate saidat least one row of contact pads and said ground plane; a plurality ofwire bonds connecting various ones of said semiconductor die, saidpower/ground ring and said row of contact pads; and an overmold coveringsaid semiconductor die and all expect one exposed surface of said row ofcontact pads and said ground plane.
 10. The leadless plastic chipcarrier of claim 9 , wherein said at least one row of contact padscomprises a plurality of metal layers deposited to form a rivet shape inprofile.
 11. The leadless plastic chip carrier of claim 9 , wherein saidat least one row of contact pads is round.
 12. The leadless plastic chipcarrier of claim 9 , wherein said at least one row of contact pads isrectangular.
 13. The leadless plastic chip carrier of claim 9 , whereinsaid at least one row of contact pads is recessed into said overmold toform a plurality of etch down cavities.
 14. The leadless plastic chipcarrier of claim 13 , further including a plurality of solder ballswithin said etch down cavities and connected to said at least one row ofcontact pads.
 15. The leadless plastic chip carrier of claim 1 , whereinan outer edge of said ground plane conforms to an interlock pattern. 16.The leadless plastic chip carrier of claim 10 , wherein said pluralityof metal layers comprises successive layers of Au, Ni, Cu, Ni and Au.17. The leadless plastic chip carrier of claim 10 , wherein saidplurality of metal layers comprises successive layers of Au, Ni, Cu, andAg.
 18. The leadless plastic chip carrier of claim 10 , wherein saidplurality of metal layers comprises successive layers of Tin, Cu, Ni andAu.
 19. The leadless plastic chip carrier of claim 10 , wherein saidplurality of metal layers comprises successive layers of Tin, Cu, andAg.
 20. The leadless plastic chip carrier on claim 10 wherein the etchedstrip is passed through a hot air level soldering step to coat theexternal metal surfaces with a thin uniform layer of solder.